1. Field of the Invention
The present invention relates to a method for the reversible oxidation protection of microcomponents, in particular of semiconductor components.
2. Description of the Related Art
Although applicable in principle to any desired components, the present invention and the problem area on which it is based are explained below with regard to integrated circuits, and in particular memory circuits using silicon technology that are fabricated using so-called STI technology (STI=Shallow Trench Isolation).
In modern memory chips, a multiplicity of trenches are introduced into a semiconductor substrate. These trenches serve on the one hand for isolating adjacent memory cells, for which purpose an STI process (STI=Shallow Trench Isolation) is used. On the other hand, individual trench capacitors are embedded as part of a memory cell in the trenches, for which purpose a so-called deep trench (DT) technology is used. In the case of the STI process, the trenches are filled with a dielectric material, for example silicon dioxide. The trenches are filled using known filling methods, for example, such as the HDP method (HDP=High Density Plasma) or the SOD method (SOD=Spin-on Dielectric), which is a further development of the generally known spin-on-glass method (SOG). In the case of spun-on insulation layers, such as the aforementioned SOG or SOD, these insulation layers flow and thus fill the trench.
With the increasing integration of modern memory chips and the accompanying reduction of the feature sizes, the trenches have an ever higher aspect ratio, with the consequence that the filling properties and thus the quality of the insulation material introduced into the trench no longer satisfy the demands for modern memory chips without further measures. In particular for modern technologies in the so-called “deep sub-micron” range, that is to say for feature sizes of 100 nm or less, there is the problem that the methods (HDP, SOD) just mentioned require a subsequent thermal process in order that the trenches are filled in a manner free of cavities. By means of this thermal process (annealing), the insulation material introduced into the trenches is densified and subsequently has the desired properties. This thermal process is carried out at relatively high temperatures in the region of approximately 950° C. in an oxidizing atmosphere. On account of the relatively high temperatures and the oxidizing atmosphere, however, there is the problem that the silicon substrate is thereby simultaneously oxidized. Particularly in the case of such semiconductor components which have very small feature sizes, the feature sizes, which are small anyway, are reduced further in an undesirable manner by means of the undesirable oxidation of the trench walls during the thermal step.
In order to prevent such undesirable oxidation of the silicon substrate by the thermal process, a protective layer acting as a diffusion barrier is typically applied to the silicon substrate. This protective layer thus prevents oxygen molecules from diffusing to the interface of the silicon substrate and thus protects the silicon substrate against the undesirable oxidation. A thin silicon nitride layer, which is generally also referred to as a nitride liner or as a nitride layer, is preferably used as the protective layer.
The nitride layer, however, has advantages only during the fabrication process, but it has electrical disadvantages on the finished semiconductor device and these disadvantages may adversely affect the electrical properties of the component. What has been found to be problematic when using a thin nitride layer in the STI trench is the fact that although this nitride layer protects the silicon substrate against an undesirable oxidation during the thermal process for densifying the insulation material, nitride layers tend to retain charges in the semiconductor component. This effect is generally also referred to as “charge trapping”. These charges trapped by the nitride layer form parasitic capacitances which have an increasingly negative influence primarily as the feature sizes become increasingly smaller. In particular, these charges and the parasitic capacitances brought about thereby may result in difficult-to-control influencing of the electrical parameters of the semiconductor component.
By adapting the process parameters of the thermal process, for example by reducing the temperature, by reducing the partial pressure of the oxidizing components, by employing low pressure annealing and the like, the problem mentioned can admittedly be reduced, but not completely eliminated. Furthermore, although the adaptation of the parameters of the thermal process just mentioned realizes a reduction of the oxidation of the silicon substrate, this is also accompanied by a deterioration in the properties of the insulation material.